1. Field
The present disclosure relates to a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
As one of the scaling technologies to increase the density of semiconductor devices, the multi-gate transistor has been suggested, in which silicon bodies in a fin or nano wire shape are formed on a substrate, with gates then being formed on surfaces of the silicon bodies. Such a multi-gate transistor allows easy scaling, as it uses a three-dimensional channel. Further, current control capability can be enhanced without requiring increased gate length of the multi-gate transistor. Furthermore, it is possible to effectively suppress short channel effect (SCE) which is the phenomenon that the electric potential of the channel region is influenced by the drain voltage.